View M48T129V_2155206.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/30 may 2002 m48t129y M48T129V 5.0 or 3.3v, 1 mbit (128 kbit x 8) timekeeper ? sram features summary n integrated, ultra low power sram, real time clock, power-fail control circuit, battery, and crystal n year 2000 compliant n bcd coded century, year, month, day, date, hours, minutes, and seconds n battery low warning flag n automatic power-fail chip deselect and write protection n two write protect voltages: (v pfd = power-fail deselect voltage) C m48t129y: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v C M48T129V: v cc = 3.0 to 3.6v 2.7v v pfd 3.0v n conventional sram operation; unlimited write cycles n software controlled clock calibration for high accuracy applications n 10 years of data retention and clock operation in the absence of power n self contained battery and crystal in dip package n microprocessor power-on reset (valid even during battery back-up mode) n programmable alarm output active in battery back-up mode n surface-mount (smt) solution (figure 2) includes a 44-pin soic and a 32-lead tsop (snaphat ? top to be ordered separately) n soic package provides direct connection for a snaphat top which contains the battery and crystal n snaphat housing (battery/crystal) is replaceable figure 1. 32-pin module figure 2. surface-mount (smt) solution pmdip32 (pm) module 32 1 tsop32 (n) (8 x 20mm) snaphat (sh) crystal / battery soh44 (m)
m48t129y, M48T129V 2/30 table of contents description ....................................................................4 logicdiagram(figure3.).........................................................4 signalnames(table1.)..........................................................4 32-pin module connections (figure 4.) ...............................................5 blockdiagram(figure5.).........................................................5 hardware hookup for surface-mount (smt) solution (figure 6.) . . . ........................6 maximumrating.................................................................7 absolutemaximumratings(table2.) ...............................................7 dc and ac parameters. . ........................................................8 operating and ac measurement conditions (table 3.) ..................................8 ac testing load circuit (figure 7.) ..................................................8 capacitance (table 4.) . . . ........................................................8 dccharacteristics(table5.) ......................................................9 operatingmodes..............................................................10 operating modes (table 6.) .......................................................10 readmode...................................................................11 chip enable or output enable controlled, read mode ac waveforms (figure 8.). . ..........11 addresscontrolled,readmodeacwaveforms(figure9.).............................11 readmodeaccharacteristics(table7.)...........................................12 writemode..................................................................13 write enable controlled, write ac waveforms (figure 10.) ...........................13 chipenablecontrolled,writeacwaveforms(figure11.).............................13 writemodeaccharacteristics(table8.) ..........................................14 dataretentionmode............................................................15 powerdown/upaccharacteristics(table9.)........................................15 powerdown/uptrippointsdccharacteristics(table10.)..............................16
3/30 m48t129y, M48T129V clockoperations.............................................................16 timekeeper? registers. .......................................................16 reading the clock . .............................................................16 settingtheclock...............................................................16 stopping and starting the oscillator ................................................16 timekeeper? register map (table 11.) . ..........................................17 calibratingtheclock............................................................18 settingthealarmclock..........................................................18 alarminterruptresetwaveform(figure13.).........................................19 alarm repeat mode (table 12.) . . .................................................19 back-upmodealarmwaveforms(figure14.) ........................................20 watchdogtimer ...............................................................20 power-onreset................................................................21 batterylowwarning............................................................21 initialpower-ondefaults.........................................................21 crystalaccuracyacrosstemperature(figure15.) ....................................21 calibrationwaveform(figure16.) .................................................22 v cc noise and negative going transients . ..........................................22 supplyvoltageprotection(figure17.)..............................................22 partnumbering ...............................................................23 snaphatbatterytable(table14.)................................................23 package mechanical information . . . ..........................................24 revisionhistory...............................................................29
m48t129y, M48T129V 4/30 description the m48t129y/v timekeeper ? ram is a 128 kb x 8 non-volatile static ram and real-time clock with programmable alarms and a watchdog timer. the special dip package provides a fully in- tegrated battery back-up memory and real-time clock solution. the m48t129y/v directly replaces industry standard 128 kb x 8 sram. it also pro- vides the non-volatility of flash without any re- quirement for special write timing or limitations on the number of writes that can be performed. for surface-mount environments st provides a solution consisting of a 44-pin, 330mil soic time- keeper supervisor (m48t 201v/y) and a 32- pin tsop (8 x 20mm) lpsram (m68z128/w) packages. the 44-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat ? housing con- taining the battery. the unique design allows the snaphat battery package to be mounted on top of the soic pack- age after the completion of the surface-mount pro- cess. insertion of the snaphat housing after reflow prevents potential battery damage due to the high temperatures required for device surface- mounting. the snaphat housing is keyed to pre- vent reverse insertion. the snaphat battery package is shipped sepa- rately in plastic anti-static tubes or in tape & reel form. the part number is m4txx-br12sh1 (see table 14, page 23). the 32-pin, 600mil dip hybrid houses a controller chip, sram, quartz crystal, and a long life lithium button cell in a single package. figure 3. logic diagram table 1. signal names ai02260 17 a0-a16 dq0-dq7 v cc m48t129y M48T129V g v ss 8 e w rst irq/ft a0-a16 address inputs dq0-dq7 data inputs / outputs e chip enable input g output enable input w write enable input rst reset output (open drain) irq /ft interrupt / frequency test output (open drain) v cc supply voltage v ss ground
5/30 m48t129y, M48T129V figure 4. 32-pin module connections figure 5. block diagram a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a15 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a16 rst v cc ai02261 10 1 2 5 6 7 8 9 11 12 13 14 15 16 30 29 26 25 24 23 22 21 20 19 18 17 a12 a14 w irq/ft 3 4 28 27 32 31 m48t129y M48T129V ai02583 lithium cell oscillator and clock chain v pfd v cc v ss 32,768 hz crystal voltage sense and switching circuitry 16 x 8 timekeeper registers 131,056 x 8 sram array a0-a16 dq0-dq7 e w g power rst irq/ft
m48t129y, M48T129V 6/30 figure 6. hardware hookup for surface-mount (smt) solution notes:for pin connections, see individual data sheets for m48t201y/v and m68z128/w at www.st.com. the chip enable access time of the external sram will be the combination of the chip enable access for the sram itself, plus the chip enable propagation delay t epd for the m48t201y/v. 1. for 5v, m48t129y (m48t201y + m68z128). for 3.3v, M48T129V (m48t201v + m68z128w). 2. snaphat top ordered separately. ai03632 32,768 hz crystal lithium cell a0-a16 dq0-dq7 e v cc w g wdi a18 a17 rstin1 rstin2 v ss e w g v cc v ss a0-a16 dq0-dq7 0.1 m f 0.1 m f 5v e con g con rst irq/ft sqw m48t201y/v (1) m68z128/w (2) v out snaphat (2) battery/crystal
7/30 m48t129y, M48T129V maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). 2. for so package: reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 to 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to v cc +0.3 v v cc supply voltage m48t129y C0.3 to 7.0 v M48T129V C0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
m48t129y, M48T129V 8/30 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 7. ac testing load circuit note: excluding open drain output pins; 50pf for M48T129V. table 4. capacitance note: 1. effective capacitance measured with power supply at 5v (m48t129y) or 3.3v (M48T129V); sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m48t129y M48T129V unit supply voltage (v cc ) 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) 0to70 0to70 c load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai01803c c l = 100pf or 50pf c l includes jig capacitance 650 w device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 20 pf c io (3) input / output capacitance 20 pf
9/30 m48t129y, M48T129V table 5. dc characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. outputs deselected. symbol parameter test condition (1) m48t129y M48T129V unit C70 C85 min max min max i li (2) input leakage current 0v v in v cc 2 2 a i lo (2) output leakage current 0v v out v cc 2 2 a i cc supply current outputs open 95 50 ma i cc1 supply current (standby) ttl e =v ih 84ma i cc2 supply current (standby) cmos e =v cc C 0.2v 43ma v il input low voltage C0.3 0.8 C0.3 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v v oh output high voltage i oh = C1ma 2.4 2.2 v
m48t129y, M48T129V 10/30 operating modes figure 5, page 5 illustrates the static memory array and the quartz controlled clock oscillator. the clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. the nine clock bytes (1ffffh- 1fff9h and 1fff1h) are not the actual clock counters, they are memory locations consisting of biport? read/write memory cells within the static ram array. the m48t129y/v includes a clock control circuit which updates the clock bytes with current infor- mation once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. byte 1fff8h is the clock control register. this byte con- trols user access to the clock information and also stores the clock calibration setting. byte 1fff7h contains the watchdog timer setting. the watchdog timer can generate either a reset or an interrupt, depending on the state of the watch- dog steering bit (wds). bytes 1fff6h-1fff2h include bits that, when programmed, provide for clock alarm functionality. alarms are activated when the register content matches the month, date, hours, minutes, and seconds of the clock registers. byte 1fff1h contains century informa- tion. byte 1fff0h contains additional flag informa- tion pertaining to the watchdog timer, the alarm condition and the battery status. the m48t129y/v also has its own power-fail detect circuit. this control circuitry constantly monitors the supply voltage for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the timekeeper ? register data and external sram, providing data security in the midst of un- predictable system operation. as v cc falls below battery back-up switchover voltage (v so ), the control circuitry automatically switches to the bat- tery, maintaining data and clock operation until valid power is restored. table 6. operating modes note: x = v ih or v il ;v so = battery back-up switchover voltage. 1. see table 10, page 16 for details. mode v cc e g w dq0-dq7 power deselect 4.5 to 5.5v or 3.0 to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
11/30 m48t129y, M48T129V read mode the m48t129y/v is in the read mode whenever w (write enable) is high and e (chip enable) is low. the unique address specified by the 17 ad- dress inputs defines which one of the 131,072 bytes of data is to be accessed. valid data will be available at the data i/o pins within t avqv (ad- dress access time) after the last address input signal is stable, providing the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access times (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for t axqx (output data hold time) but will go indeterminate until the next address access. figure 8. chip enable or output enable controlled, read mode ac waveforms figure 9. address controlled, read mode ac waveforms ai01197 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a16 e g dq0-dq7 valid ai02324 tavav tavqv taxqx data valid a0-a16 dq0-dq7 valid data valid
m48t129y, M48T129V 12/30 table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. symbol parameter (1) m48t129y M48T129V unit C70 C85 min max min max t avav read cycle time 70 85 ns t av qv address valid to output valid 70 85 ns t elqv chip enable low to output valid 70 85 ns t glqv output enable low to output valid 40 55 ns t elqx (2) chip enable low to output transition 5 5 ns t glqx (2) output enable low to output transition 5 5 ns t ehqz (2) chip enable high to output hi-z 25 30 ns t ghqz (2) output enable high to output hi-z 25 30 ns t axqx address transition to output transition 5 5 ns
13/30 m48t129y, M48T129V write mode the m48t129y/v is in the write mode whenever w (write enable) and e (chip enable) are low state after the address inputs are stable. the start of a write is referenced from the latter occurring falling edge of w or e .awriteistermi- nated by the earlier rising edge of w or e . the ad- dresses must be held valid throughout the cycle. e or w must return high for a minimum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g alowonw will disable the outputs t wlqz after w falls. figure 10. write enable controlled, write ac waveforms figure 11. chip enable controlled, write ac waveforms ai02382 tavav twhax tdvwh data input a0-a16 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai02582 tavav tehax tdvwh a0-a16 e w dq0-dq7 valid tavel tavwl teleh twhdx data input
m48t129y, M48T129V 14/30 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48t129y M48T129V unit C70 C85 min max min max t avav write cycle time 70 85 ns t avwl address valid to write enable low 0 0 ns t avel address valid to chip enable low 0 0 ns t wlwh write enable pulse width 50 60 ns t eleh chip enable low to chip enable high 55 65 ns t whax write enable high to address transition 5 5 ns t ehax chip enable high to address transition 10 15 ns t dvwh input valid to write enable high 30 35 ns t dveh input valid to chip enable high 30 35 ns t whdx write enable high to input transition 5 5 ns t ehdx chip enable high to input transition 10 15 ns t wlqz (2,3) write enable low to output hi-z 25 30 ns t av wh address valid to write enable high 60 70 ns t av eh address valid to chip enable high 60 70 ns t whqx (2,3) write enable high to output transition 5 5 ns
15/30 m48t129y, M48T129V data retention mode with valid v cc applied, the m48t129y/v operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically deselect, write protecting itself when v cc falls between v pfd (max), v pfd (min) win- dow. all outputs become high impedance and all inputs are treated as don't care. note: a power failure during a write cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48t129y/v may re- spond to transient noise spikes on v cc that cross into the deselect window during the time the de- vice is sampling v cc . therefore, decoupling of the power supply lines is recommended. when v cc drops below v so , the control circuit switches power to the internal battery, preserving data and powering the clock. the internal energy source will maintain data in the m48t129y/v for an accumulated period of at least 10 years at room temperature. as system power rises above v so , the battery is disconnected, and the power supply is switched to external v cc . deselect continues for t rec after v cc reaches v pfd (max). for a further more detailed review of lifetime calculations, please see application note an1012. figure 12. power down/up mode ac waveforms table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200ms after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. symbol parameter (1) min max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time m48t129y 10 s M48T129V 150 s t r v pfd (min) to v pfd (max) v cc rise time 0s t rb v ss to v pfd (min) v cc rise time 1s t rec v pfd (max) to rst high 40 200 ms ai01805 v cc inputs outputs don't care high-z tf tfb tr trb valid valid recognized recognized v pfd (max) v pfd (min) v so trec rst
m48t129y, M48T129V 16/30 table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a =0to70c;v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 3. at 25c. clock operations timekeeper ? registers the m48t129y/v offers 16 internal registers which contain timekeeper, alarm, watc hdog, interrupt, flag, and control data. these registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport timekeeper cells). the external copies are independent of internal func- tions except that they are updated periodically by the simultaneous transfer of the incremented inter- nal copy. timekeeper and alarm registers store data in bcd. reading the clock updates to the tim ekeeper ? registers should be halted before clock data is read to prevent reading data in transition. the biport? time- keeper cells in the ram array are only data reg- isters and not the actual clock counters, so updating the registers can be halted without dis- turbing the clock itself. updating is halted when a '1' is written to the read bit, d6 in the control register (1fff8h). as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and time that were current at the moment the halt command was is- sued. all of the timekeeper registers are updat- ed simultaneously. a halt will not interrupt an update in progress. updating occurs 1 second af- ter the read bit is reset to a '0.' setting the clock bit d7 of the control register (1fff8h) is the writebit.settingthewritebittoa'1,'likethe read bit, halts updates to the time keeper reg- isters. the user can then load them with the cor- rect day, date, and time data in 24 hour bcd format (see table 11, page 17). resetting the write bit to a '0' then transfers the values of all time registers (1ffffh-1fff9h, 1fff1h) to the actual timekeeper c ounters and allows normal operation to resume. after the write bit is reset, the next clock update will occur approximately one second later. note: upon power-up following a power failure, both the write bit and the read bit will be reset to '0.' stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit is located at bit d7 within 1fff9h. setting it to a '1' stops the oscillator. when reset to a '0', the m48t129y/v oscillator starts within one second. note: it is not necessary to set the write bit when setting or resetting the frequency test bit (ft) or the stop bit (st). symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage m48t129y 4.2 4.35 4.5 v M48T129V 2.7 2.9 3.0 v v so battery back-up switchover voltage m48t129y 3.0 v M48T129V v pfd C100mv t dr (3) expected data retention time 10 years
17/30 m48t129y, M48T129V table 11. timekeeper ? register map keys: s = sign bit ft = frequency test bit r = read bit w=writebit st = stop bit 0=mustbesetto'0' y='1'or'0 bl = battery low (read only) af = alarm flag (read only) wds = watchdog steering bit bmb0-bmb4 = watchdog multiplier bits rb0-rb1 = watchdog resolution bits afe = alarm flag enable abe = alarm in battery back-up mode enable rpt1-rpt5 = alarm repeat mode bits wdf = watchdog flag (read only) address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 1ffffh 10 years year year 00-99 1fffeh 0 0 0 10 m month month 01-12 1fffdh 0 0 10 date date date 01-31 1fffch 0 ft 0 0 0 day of week day 01-07 1fffbh 0 0 10 hours hours (24 hour format) hours 00-23 1fffah 0 10 minutes minutes minutes 00-59 1fff9h st 10 seconds seconds seconds 00-59 1fff8h w r s calibration control 1fff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 1fff6h afe 0 abe al 10m alarm month a month 01-12 1fff5h rpt4 rpt5 al 10 date alarm date al date 01-31 1fff4h rpt3 0 al 10 hours alarm hours a hours 00-23 1fff3h rpt2 al 10 minutes alarm minutes a min 00-59 1fff2h rpt1 al 10 seconds alarm seconds a sec 00-59 1fff1h 1000 year 100 year century 00-99 1fff0h wdf af 0 bl y y y y flag
m48t129y, M48T129V 18/30 calibrating the clock the m48t129y/v is driven by a quartz controlled oscillator with a nominal frequency of 32,768hz. the devices are factory calibrated at 25c and tested for accuracy. clock accuracy will not ex- ceed 35 ppm (parts per million) oscillator frequen- cy error at 25c, which equates to about 1.53 minutes per month (see figure 15, page 21). when the calibration circuit is properly employed, accuracy improves to better than +1/C2 ppm at 25c. the oscillation rate of crystals changes with temperature. the m48t129y/v design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in fig- ure 16, page 22. the number of times pulses are blanked (subtract- ed, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control regis- ter. adding counts speeds the clock up, subtract- ing counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register 1fff8h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive cal- ibration, '0' indicates negative calibration. calibra- tion occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modi- fied; if a binary 6 is loaded, the first 12 will be af- fected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 os- cillator cycles for every 125, 829, 120 actual oscil- lator cycles, that is +4.068 or C2.034 ppm of adjustment per calibration step in the calibration register. assuming that the oscillator is running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or C5.35 seconds per month which corresponds to a total range of +5.5 or C2.75 minutes per month. figure 16, page 22 illustrates a tim ekeeper ? calibra- tion waveform. two methods are available for ascertaining how much calibration a given m48t129y/v may re- quire. the first involves setting the clock, letting it run for a month and comparing it to a known accu- rate reference and recording deviation over a fixed period of time. calibration values, including the number of sec- onds lost or gained in a given period, can be found in the application note an934, tim ekeeper calibration. this allows the designer to give the end user the ability to calibrate the clock as the environment re- quires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq /ft pin. the pin will toggle at 512hz, when the stop bit (st, d7 of 1fff9h) is '0,' the frequency test bit (ft, d6 of 1fffch) is '1,' the alarm flag enable bit (afe, d7 of 1fff6h) is '0,' and the watchdog steering bit (wds, d7 of 1fff7h) is '1' or the watchdog register (1fff7h = 0) is reset. note: a 4 second settling time must be allowed before reading the 512hz output. any deviation from 512hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124hz would indicate a +20 ppm oscillator frequency error, requiring a C10 (wr001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequen- cy. the irq /ft pin is an open drain output which re- quires a pull-up resistor for proper operation. a 500-10k w resistor is recommended in order to control the rise time. the ft bit is cleared on pow- er-up. setting the alarm clock registers 1fff6h-1fff2h contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every month, day, hour, minute, or second. it can also be pro- grammed to go off while the m48t129y/v is in the battery back-up to serve as a system wake-up call. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 12, page 19 shows the possi- ble configurations. codes not listed in the table de- fault to the once per second mode to quickly alert the user of an incorrect alarm setting. note: user must transition address (or toggle chip enable) to see flag bit change.
19/30 m48t129y, M48T129V when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condi- tion activates the irq /ft pin. to disable alarm, write 0 to the alarm date register and rpt1-5. the irq /ft output is cleared by a read to the flags register as shown in figure 13. a subse- quent read of the flags register is necessary to see that the value of the alarm flag has been re- set to '0.' the irq /ftpincanalsobeactivatedinthebat- tery back-up mode. the irq /ft will go low if an alarm occurs and both abe (alarm in battery back-up mode enable) and afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot-up to determine if an alarm was generated while the m48t129y/v was in the deselect mode during power-up. figure 14, page 20 illustrates the back-up mode alarm timing. figure 13. alarm interrupt reset waveform table 12. alarm repeat mode rpt5 rpt4 rpt3 rpt2 rpt1 alarm activated 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 1 1 0 0 0 once per day 1 0 0 0 0 once per month 0 0 0 0 0 once per year ai02581 ad0-ad7 active flag bit address 1ff0h irq/ft high-z 15ns min
m48t129y, M48T129V 20/30 figure 14. back-up mode alarm waveforms watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 1fff7h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolution, where 00 = 1/16 second, 01 = 1/4 sec- ond, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). note: accuracy of timer is a function of the select- ed resolution. if the processor does not reset the timer within the specified period, the m48t129y/v sets the wdf (watchdog flag) and generates a watchdog inter- rupt or a microprocessor reset. wdf is reset by reading the flags register (address 1fff0h). the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a '0,' the watchdog will activate the irq /ft pin when timed-out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for 40 to 200 ms. the watchdog register and the ft bit will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog tim- er can be reset by two methods: 1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi); or 2. the microprocessor can perform a write of the watchdog register. the time-out period then starts over. the wdi pin shouldbetiedtov ss if not used. the watchdog will be reset on each transition (edge) seen by the wdi pin. in the order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effec- tively restarting the count-down cycle. should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog regis- ter in order to clear the irq /ft pin. this will also disable the watchdog function until it is again pro- grammed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 1fff0h). the watchdog function is automatically disabled upon power-down and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft pin and the frequency test function is activated, the watchdog or alarm function prevails and the frequency test function is denied. ai01678c v cc irq/ft high-z v pfd (max) v pfd (min) afe bit in interrupt register af bit in flags register high-z v so trec
21/30 m48t129y, M48T129V power-on reset the m48t129y/v continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appro- priate pull-up resistor to v cc should be chosen to control the rise time. battery low warning the m48t129y/v automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 1fff0h, will be asserted if the battery voltage is found to be less than approximately 2.5v. if a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. if a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. however, data is not com- promised due to the fact that a nominal v cc is supplied. the m48t129y/v only monitors the battery when a nominal v cc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. initial power-on defaults upon application of power to the device, the fol- lowing register bits are set to a '0' state: wds, bmb0-bmb4, rb0,rb1, afe, abe, w, r and ft. figure 15. crystal accuracy across temperature ai00999 C160 0 10203040506070 frequency (ppm) temperature c 80 C10 C20 C30 C40 C100 C120 C140 C40 C60 C80 20 0 C20 d f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c
m48t129y, M48T129V 22/30 figure 16. calibration waveform v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sultinginspikesonthev cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (see figure 17) is recommended in order to provide the needed fil- tering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, st recommends connecting a schottky diode from v cc to v ss (cathode con- nected to v cc , anode to v ss ). (schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface-mount). figure 17. supply voltage protection ai00594b normal positive calibration negative calibration ai02169 v cc 0.1 m f device v cc v ss
23/30 m48t129y, M48T129V part numbering table 13. ordering information scheme note: 1. the soic package (soh44) requires the battery package (snaphat ? ) which is ordered separately under the part number m4txx-br12sh in plastic tube or m4txx-br12shtr in tape & reel form. caution : do not place the snaphat battery package m4txx-br12sh in conductive foam as it will drain the lithium button-cell battery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 14. snaphat battery table example: m48t 129y C70 pm 1 device type m48t supply voltage and write protect voltage 129y = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v 129v = v cc = 3.0 to 3.6v; v pfd = 2.7 to 3.0v speed C70 = 70ns (for m48t129y) C85 = 85ns (for M48T129V) package (1) pm = pmdip32 temperature range 1 = 0 to 70c part number description package m4t28-br12sh lithium battery (48mah) snaphat sh m4t32-br12sh lithium battery (120mah) snaphat sh
m48t129y, M48T129V 24/30 package mechanical information figure 18. pmdip32 C 32-pin plastic dip module, package outline note: drawing is not to scale. table 15. pmdip32 C 32-pin plastic dip module, package mechanical data symb mm inches typ min max typ min max a 9.27 9.52 0.365 0.375 a1 0.38 C 0.015 C b 0.43 0.59 0.017 0.023 c 0.20 0.33 0.008 0.013 d 42.42 43.18 1.670 1.700 e 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 ea 14.99 16.00 0.590 0.630 l 3.05 3.81 0.120 0.150 s 1.91 2.79 0.075 0.110 n32 32 pmdip a1 a l be1 d e n 1 ea e3 s c
25/30 m48t129y, M48T129V figure 19. tsop32 C 32-lead plastic thin small outline, 8 x 20 mm, package outline note: drawing is not to scale. table 16. tsop32 C 32-lead plastic thin small outline, 8 x 20 mm, package mechanical data symbol mm inch typ min max typ min max a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 0.950 1.050 0.0374 0.0413 b 0.150 0.270 0.0059 0.0106 c 0.100 0.210 0.0039 0.0083 d 19.800 20.200 0.7795 0.7953 d1 18.300 18.500 0.7205 0.7283 e 0.500 C C 0.0197 C C e 7.900 8.100 0.3110 0.3189 l 0.500 0.700 0.0197 0.0276 a 0 5 0 5 cp 0.100 0.0039 n32 1.3 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
m48t129y, M48T129V 26/30 figure 20. sh C 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 17. sh C 4-pin snaphat housing for 48mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
27/30 m48t129y, M48T129V figure 21. sh C 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 18. sh C 4-pin snaphat housing for 120mah battery & crystal, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
m48t129y, M48T129V 28/30 figure 22. soh44 C 44-lead plastic small outline, 4-socket battery, snaphat, package outline note: drawing is not to scale. table 19. soh44 C 44-lead plastic small outline, 4-socket battery, snaphat, package mech. data symb mm inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.46 0.014 0.018 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 0.81 C C 0.032 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n44 44 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
29/30 m48t129y, M48T129V revision history table 20. revision history date revision details april 2000 chipset data sheet - first issue 06/22/01 reformatted; added temperature information (table 4, 5, 7, 8, 9, 10) 08/01/01 added value to ac testing load circuit (figure 7) 08/06/01 fix text and table for setting the alarm clock (table 12) 08/13/01 fix error in setting the alarm clock text 11/07/01 remove chipset option from ordering information (table 13) 03/26/02 replace chipset term with solution, as well as related changes throughout the document 05/20/02 modify reflow time and temperature footnotes (table 2)
m48t129y, M48T129V 30/30 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

▲Up To Search▲

Price & Availability of M48T129V

	To Download M48T129V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .